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| ispgdx ? 160v/va device datasheet june 2010 select devices discontinued! product change notification (pcn) #09-10 has been issued to discontinue select devices in this data sheet. the original datasheet pages have not been modi fied and do not reflect those changes. please refer to the table below for refe rence pcn and current product status. product line ordering part number product status reference pcn ispgdx160v-5b272 ispgdx160v-7b272 discontinued pcn#09-10 ispgdx160v-5b208 ispgdx160v-7b208 ispgdx160v-5q208 ispgdx160v-7q208 ispgdx160v ispgdx160v-7q208i active / orderable ispgdx160va-3b272 ispgdx160va-5b272 ispgdx160va-7b272 ispgdx160va-5b272i ispgdx160va-7b272i ispgdx160va-9b272i discontinued pcn#09-10 ispgdx160va-3q208 ispgdx160va-5q208 ispgdx160va-7q208 ispgdx160va-5q208i ispgdx160va-7q208i ispgdx160va-9q208i ispgdx160va-3b208 ispgdx160va-3bn208 ispgdx160va-5b208 ispgdx160va-5bn208 ispgdx160va-7b208 ispgdx160va-7bn208 ispgdx160va-5b208i ispgdx160va-5bn208i ispgdx160va-7b208i ispgdx160va-7bn208i ispgdx160va-9b208i ispgdx160va ispgdx160va-9bn208i active / orderable 5555 n.e. moore ct. z hillsboro, oregon 97124-6421 z phone (503) 268-8000 z fax (503) 268-8347 internet: http://www.latticesemi.com
1 ispgdx 160v/va in-system programmable 3.3v generic digital crosspoint functional block diagram features in-system programmable generic digital crosspoint family advanced architecture addresses programmable pcb interconnect, bus interface integration and jumper/switch replacement ??ny input to any output?routing ?fixed high or low output option for jumper/dip switch emulation ?space-saving pqfp and bga packaging ?dedicated ieee 1149.1-compliant boundary scan test high performance e 2 cmos technology ?3.3v core power supply ?3.5ns input-to-output/3.5ns clock-to-output delay* 250mhz maximum clock frequency* ttl/3.3v/2.5v compatible input thresholds and output levels (individually programmable)* ?low-power: 16.5ma quiescent icc* ?24ma i ol drive with programmable slew rate control option pci compatible drive capability* ?schmitt trigger inputs for noise immunity ?electrically erasable and reprogrammable ?non-volatile e 2 cmos technology ispgdxv offers the following advantages ?3.3v in-system programmable using boundary scan test access port (tap) ?change interconnects in seconds flexible architecture ?combinatorial/latched/registered inputs or outputs ?individual i/o tri-state control with polarity control ?dedicated clock/clock enable input pins (four) or programmable clocks/clock enables from i/o pins (40) ? single level 4:1 dynamic path selection (tpd = 3.5ns) ?programmable wide-mux cascade feature supports up to 16:1 mux ?programmable pull-ups, bus hold latch and open drain on i/o pins ?outputs tri-state during power-up (?ive insertion friendly) lead-free package options * ?a?version only global routing pool (grp) i/o cells i/o pins b boundary scan control i/o cells isp control i/o pins a i/o pins c i/o pins d description the ispgdxv/va architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface require- ments including: multi-port multiprocessor interfaces ? ide data and address bus multiplexing (e.g. 16:1 high-speed bus mux) programmable control signal routing (e.g. interrupts, dmareqs, etc.) board-level pcb signal routing for prototyping or programmable bus interfaces the devices feature fast operation, with input-to-output signal delays (tpd) of 3.5ns and clock-to-output delays of 3.5ns. the architecture of the devices consists of a series of programmable i/o cells interconnected by a global rout- ing pool (grp). all i/o pin inputs enter the grp directly or are registered or latched so they can be routed to the required i/o outputs. i/o pin inputs are defined as four sets (a,b,c,d) which have access to the four mux inputs gdx160va_06 copyright ?2004 lattice semiconductor corporation. all brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2004 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com lead- free package options available! select devices discontinued 2 specifications ispgdx160v/va description (continued) found in each i/o cell. each output has individual, pro- grammable i/o tri-state control (oe), output latch clock (clk), clock enable (clken), and two multiplexer con- trol (mux0 and mux1) inputs. polarity for these signals is programmable for each i/o cell. the mux0 and mux1 inputs control a fast 4:1 mux, allowing dynamic selection of up to four signal sources for a given output. a wider 16:1 mux can be implemented with the mux expander feature of each i/o and a propagation delay increase of 2.0ns. oe, clk, clken, and mux0 and mux1 inputs can be driven directly from selected sets of i/o pins. optional dedicated clock input pins give minimum clock- to-output delays. clk and clken share the same set of i/o pins. clken disables the register clock when clken = 0. through in-system programming, connections between i/o pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. in keeping with its data path application focus, the ispgdxv devices contain no programmable logic arrays. all input pins include schmitt trigger buffers for noise immunity. these connections are programmed into the device using non-volatile e 2 cmos technology. non-volatile technology means the device configuration is saved even when the power is removed from the device. in addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. that is, any i/o pin configured as an input can drive one or more i/o pins configured as outputs. the device pins also have the ability to set outputs to fixed high or low logic levels (jumper or dip switch mode). device outputs are specified for 24ma sink and 12ma source current (at jedec lvttl levels) and can be tied together in parallel for greater drive. on the ispgdxva, each i/o pin is individually programmable for 3.3v or 2.5v output levels as described later. program- mable output slew rate control can be defined independently for each i/o pin to reduce overall ground bounce and switching noise. all i/o pins are equipped with ieee1149.1-compliant boundary scan test circuitry for enhanced testability. in addition, in-system programming is supported through the test access port via a special set of private com- mands. the ispgdxv i/os are designed to withstand ?ive inser- tion?system environments. the i/o buffers are disabled during power-up and power-down cycles. when design- ing for ?ive insertion,?absolute maximum rating conditions for the vcc and i/o pins must still be met. table 1. ispgdxv family members ispgdxva device ispgdx160va i/o pins 160 i/o-oe inputs* 40 i/o-clk / clken inputs* 40 i/o-muxsel1 inputs* 40 i/o-muxsel2 inputs* 40 bscan interface 4 reset 1 pin count/package 208-pin pqfp 208-ball fpbga 272-ball bga * the clk/clk_en, oe, mux0 and mux1 terminals on each i/o cell can each be assigned to 25% of the i/os. ** global clock pins y0, y1, y2 and y3 are multiplexed with clken0, clken1, clken2 and clken3 respectively in all devices. toe 1 dedicated clock pins** 4 epen 1 80 20 20 20 20 4 1 100-pin tqfp 1 2 1 240 60 60 60 60 4 1 388-ball fpbga 1 4 1 ispgdx80va ispgdx240va select devices discontinued 3 specifications ispgdx160v/va architecture the ispgdxv/va architecture is different from traditional pld architectures, in keeping with its unique application focus. the block diagram is shown below. the program- mable interconnect consists of a single global routing pool (grp). unlike isplsi devices, there are no pro- grammable logic arrays on the device. control signals for oes, clocks/clock enables and mux controls must come from designated sets of i/o pins. the polarity of these signals can be independently programmed in each i/o cell. each i/o cell drives a unique pin. the oe control for each i/o pin is independent and may be driven via the grp by one of the designated i/o pins (i/o-oe set). the i/o-oe set consists of 25% of the total i/o pins. boundary scan test is supported by dedicated registers at each i/o pin. in-system programming is accomplished through the standard boundary scan protocol. the various i/o pin sets are also shown in the block diagram below. the a, b, c, and d i/o pins are grouped together with one group per side. i/o architecture each i/o cell contains a 4:1 dynamic mux controlled by two select lines as well as a 4x4 crossbar switch con- trolled by software for increased routing flexiability (figure 1). the four data inputs to the mux (called m0, m1, m2, and m3) come from i/o signals in the grp and/or adjacent i/o cells. each mux data input can access one quarter of the total i/os. for example, in a 160 i/o ispgdxv, each data input can connect to one of 40 i/o pins. mux0 and mux1 can be driven by designated i/o pins called muxsel1 and muxsel2. each muxsel input covers 25% of the total i/o pins (e.g. 40 out of 160). mux0 and mux1 can be driven from either muxsel1 or muxsel2. figure 1. ispgdxv/va i/o cell and grp detail (160 i/o device) i/ocell 0 i/o cell 1 i/o cell 78 i/o cell 79 80 i/o cells boundary scan cell bypass option i/o cell n register or latch i/o pin prog. pull-up (vccio) prog. slew rate d a b clk reset q 4-to-1 mux 160 input grp inputs vertical outputs horizontal i/o cell 159 i/o cell 158 i/o cell 81 m0 i/o group a i/o group b i/o group c i/o group d m1 4x4 crossbar switch m2 m3 mux1 mux0 global reset i/o cell 80 ????? 80 i/o cells ispgdxv/va architecture enhancements over ispgdx (5v) e 2 cmos programmable interconnect logic ? logic ? 160 i/o inputs c r y0-y3 global clocks / clock_enables prog. bus hold latch clk_en from mux outputs of 2 adjacent i/o cells from mux outputs of 2 adjacent i/o cells to 2 adjacent i/o cells above to 2 adjacent i/o cells below prog. open drain 2.5v/3.3v output n+1 n+2 n-1 n-2 select devices discontinued 4 specifications ispgdx160v/va flexible mapping of muxsel x to mux x allows the user to change the mux select assignment after the ispgdxv/ va device has been soldered to the board. figure 1 shows that the i/o cell can accept (by programming the appropriate fuses) inputs from the mux outputs of four adjacent i/o cells, two above and two below. this en- ables cascading of the muxes to enable wider (up to 16:1) mux implementations. the i/o cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. as shown in figure 1, when the input control mux of the register/ latch selects the ??path, the register/latch gets its inputs from the 4:1 mux and drives the i/o output. when selecting the ??path, the register/latch is directly driven by the i/o input while its output feeds the grp. the programmable polarity clock to the latch or register can be connected to any i/o in the i/o-clk/clken set (one- quarter of total i/os) or to one of the dedicated clock input pins (y x ). the programmable polarity clock enable input to the register can be programmed to connect to any of the i/o-clk/clken input pin set or to the global clock enable inputs (clken x ). use of the dedicated clock inputs gives minimum clock-to-output delays and mini- mizes delay variation with fanout. combinatorial output mode may be implemented by a dedicated architecture bit and bypass mux. i/o cell output polarity can be programmed as active high or active low. mux expander using adjacent i/o cells the ispgdxv/va allows adjacent i/o cell muxes to be cascaded to form wider input muxes (up to 16 x 1) without incurring an additional full tpd penalty. however, there are certain dependencies on the locality of the adjacent muxes when used along with direct mux inputs. adjacent i/o cells expansion inputs muxout[n-2], muxout[n-1], muxout[n+1], and muxout[n+2] are fuse-selectable for each i/o cell mux. these expansion inputs share the same path as the standard a, b, c and d mux inputs, and allow adjacent i/o cell outputs to be directly connected without passing through the global routing pool. the relationship between the [n+i] adjacent cells and a, b, c and d inputs will vary depending on where the i/o cell is located on the physical die. the i/o cells can be grouped into ?ormal?and ?eflected?i/o cells or i/o ?emi- spheres.?these are defined as: i/o mux operation mux1 mux0 data input selected 00 m0 01 m1 11 m2 10 m3 device normal i/o cells reflected i/o cells tba tba b19-b0, a39-a20, a19-a0, d39-d20 b20-b39, c0-c19, c20-c39, d0-d19 ispgdx80va ispgdx160v/va ispgdx240va tba tba table 2 shows the relationship between adjacent i/o cells as well as their relationship to direct mux inputs. note that the mux expansion is circular and that i/o cell b20, for example, draws on i/os b19 and b18, as well as b21 and b22, even though they are in different hemi- spheres of the physical die. table 2 shows some typical cases and all boundary cases. all other cells can be extrapolated from the pattern shown in the table. d20 d19 b19 b20 a0 a39 c39 c0 d39 b0 d0 b39 i/o cell 0 i/o cell 159 i/o cell 79 i/o cell 80 i/o cell index increases in this direction i/o cell index increases in this direction figure 2. i/o hemisphere configuration of ispgdx160v/va direct and expander input routing table 2 also illustrates the routing of mux direct inputs that are accessible when using adjacent i/o cells as inputs. take i/o cell d23 as an example, which is also shown in figure 3. select devices discontinued 5 specifications ispgdx160v/va b20 b21 b22 b23 d16 d17 d18 d19 d20 d21 d22 d23 b16 b17 b18 b19 b22 b23 b24 b25 d18 d19 d20 d21 d18 d19 d20 d21 b14 b15 b16 b17 b21 b22 b23 b24 d17 d18 d19 d20 d19 d20 d21 d22 b15 b16 b17 b18 b19 b20 b21 b22 d15 d16 d17 d18 d21 d22 d23 d24 b17 b18 b19 b20 b18 b19 b20 b21 d14 d15 d16 d17 d22 d23 d24 d25 b18 b19 b20 b21 data d/ muxout data c/ muxout data b/ muxout data a/ muxout reflected i/o cells normal i/o cells table 2. adjacent i/o cells (mapping of ispgdx160v/va) it can be seen from figure 3 that if the d21 adjacent i/o cell is used, the i/o group ??input is no longer available as a direct mux input. the ispgdxv/va can implement muxes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent i/o cell outputs with direct mux inputs. any particular combination of adjacent i/o cells as mux inputs will dictate what i/o groups (a, b, c or d) can be routed to the remaining inputs. by properly choosing the adjacent i/o cells, all of the mux inputs can be utilized. s0s1 4 x 4 crossbar switch .m0 .m1 .m2 .m3 d23 i/o group a d21 mux out i/o group b d22 mux out i/o group c d24 mux out i/o group d d25 mux out ispgdx160v/va i/o cell figure 3. adjacent i/o cells vs. direct input path for ispgdx160v/va, i/o d23 special features slew rate control all output buffers contain a programmable slew rate control that provides software-selectable slew rate op- tions. open drain control all output buffers provide a programmable open-drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip open-drain or open-collector buffer. wire-or logic functions can be performed at the printed circuit board level. pull-up resistor all pins have a programmable active pull-up. a typical resistor value for the pull-up ranges from 50k? to 80k ?. output latch (bus hold) all pins have a programmable circuit that weakly holds the previously driven state when all drivers connected to the pin (including the pin's output driver as well as any other devices connected to the pin by external bus) are tristated. ispgdx160va new features unique to the ispgdx160va are user-programmable i/os supporting either 3.3v or 2.5v output voltage level options. the ispgdx160va uses a vccio pin to provide the 2.5v reference voltage when used. the ispgdx160va vccio pin occupies the same location as vcc on the ispgdx160v, allowing drop-in replacement. the ispgdx160va offers improved performance by reducing fanout delays and has pci compatible drive capability. only the ispgdx160va is available in the fastest (3.5ns) commercial speed grade and in -5,-7, and -9ns industrial grades in all packages. the ispgdx160va has a device id different from the ispgdx160v requiring that the latest lattice download software be used for programming and verification. al- though the ispgdx160va and ispgdx160v are functionally equivalent, they are not 100% jedec com- patible. all design files must be recompiled targeting the ispgdx160va. select devices discontinued 6 specifications ispgdx160v/va the ispgdxv/va family architecture has been devel- oped to deliver an in-system programmable signal routing solution with high speed and high flexibility. the devices are targeted for three similar but distinct classes of end- system applications: programmable, random signal interconnect (prsi) this class includes pcb-level programmable signal rout- ing and may be used to provide arbitrary signal swapping between chips. it opens up the possibilities of program- mable system hardware. it is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control in- puts. programmable data path (pdp) this application area includes system data path trans- ceiver, mux and latch functions. with today? 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, pcbs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. many of these applications consist of ?n-board?bus and memory inter- faces that do not require the very high drive of standard glue functions but can benefit from higher integration. therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic? solution to control logic integration. lattice? cplds make an ideal control logic complement to the ispgdxv/va in-system program- mable data path devices as shown below. data path bus #1 control inputs (from p) address inputs (from p) control outputs system clock(s) data path bus #2 configuration (switch) outputs isp/jtag interface isplsi/ ispmach device ispgdxv/va device buffers / registers decoders buffers / registers state machines figure 4. ispgdxv/va complements lattice cplds applications programmable switch replacement (psr) includes solid-state replacement and integration of me- chanical dip switch and jumper functions. through in-system programming, pins of the ispgdxv/va de- vices can be driven to high or low logic levels to emulate the traditional device outputs. psr functions do not require any input pin connections. these applications actually require somewhat different silicon features. prsi functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. the routing connections are static (determined at programming time) and each input-to-output path operates independently. as a result, there is little need for dynamic signal controls (oe, clocks, etc.). because the ispgdxv/va device will inter- face with control logic outputs from other components (such as isplsi or ispmach ) on the board (which frequently change late in the design process as control logic is finalized), there must be no restrictions on pin-to- pin signal routing for this type of application. pdp functions, on the other hand, require the ability to dynamically switch signal routing (muxing) as well as latch and tri-state output signals. as a result, the pro- grammable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external mpu or control logic. these functions are usually formulated early in the conceptual design of a product. the data path requirements are driven by the microprocessor, bus and memory architec- ture defined for the system. this part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and pcb redesign. as a result, the ability to accommodate arbitrary any pin-to-any pin re- routing is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. as a result, the ispgdxv/va architecture has been defined to support psr and prsi applications (including bidirectional paths) with no restrictions, while pdp appli- cations (using dynamic muxing) are supported with a minimal number of restrictions as described below. in this way, speed and cost can be optimized and the devices can still support the system designer? needs. the following diagrams illustrate several ispgdxv/va applications. select devices discontinued 7 specifications ispgdx160v/va figure 6. data bus byte swapper figure 7. four-port memory interface control bus data bus a data bus b oea oeb i/oa d0-7 d8-15 d8-15 d0-7 i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr oea oeb i/oa i/ob xcvr bus 4 bus 3 bus 2 bus 1 port #1 oe1 memory port oem sel0 sel1 to memory port #2 oe2 port #3 oe3 note: all oe and sel lines driven by external arbiter logic (not shown). port #4 oe4 4-to-1 16-bit mux bidirectional figure 5. address demultiplex/data buffering control bus muxed address data bus dq clk oea oeb i/oa i/ob address buffered data to memory/ per ipherals xcvr address latch applications (continued) designing with the ispgdxv/va as mentioned earlier, this architecture satisfies the prsi class of applications without restrictions: any i/o pin as a single input or bidirectional can drive any other i/o pin as output. for the case of pdp applications, the designer does have to take into consideration the limitations on pins that can be used as control (mux0, mux1, oe, clk) or data (muxa-d) inputs. the restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. the muxa-d input partitioning requires that designers consciously assign pinouts so that mux inputs are in the appropriate, disjoint groups. for example, since the muxa group includes i/o0-39 (160 i/o device), it is not possible to use i/o0 and i/o9 in the same mux function. as previously discussed, data path functions will be assigned early in the design process and these restric- tions are reasonable in order to optimize speed and cost. user electronic signature the ispgdxv/va family includes dedicated user elec- tronic signature (ues) e 2 cmos storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. the ues information is accessible through the boundary scan programming port via a specific com- mand. this information can be read even when the security cell is programmed. security the ispgdxv/va family includes a security feature that prevents reading the device program once set. even when set, it does not inhibit reading the ues or device id code. it can be erased only via a device bulk erase. select devices discontinued 8 specifications ispgdx160va absolute maximum ratings 1,2 supply voltage v cc ................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating conditions c symbol table 2-0006/gdx160va c parameter package type dedicated clock capacitance 8 units typical test conditions 1 2 7 pqfp bga, fpbga pqfp bga, fpbga i/o capacitance pf 10 pf pf 10 pf v = 3.3v, v = 2.0v v = 3.3v, v = 2.0v cc cc y i/o capacitance (t a =25 o c, f=1.0 mhz) parameter minimum maximum units erase/reprogram cycles 10,000 cycles erase/reprogram specifications symbol table 2-0005/gdx160va v cc v ccio parameter supply voltage i/o reference voltage commercial t a = 0c to +70c min. max. units 3.00 2.3 3.60 3.60 v industrial t a = -40c to +85c 3.00 3.60 v v select devices discontinued 9 specifications ispgdx160va switching test conditions input pulse levels input rise and fall time input timing reference levels output timing reference levels output load gnd to v ccio(min) < 1.5ns 10% to 90% v ccio(min) /2 v ccio(min) /2 see figure 8 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure 8) test condition r1 3.3v 2.5v r2 cl a 35pf d 35pf b 35pf 35pf active high slow slew active low c 5pf 5pf 156? 156? 156? 144? 144? 144? r1 r2 153? 153? 153? 134? 134? 134? active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a/gdx160va dc electrical characteristics for 3.3v range 1 over recommended operating conditions figure 8. test load v ccio r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213d v ol symbol 1. i/o voltage configuration must be set to vcc. table 2-0007/gdx160va v oh v ih v il parameter output low voltage output high voltage input high voltage input low voltage v cc = v cc (min) i ol = +100a i ol = +24ma i oh = -100a i oh = -12ma v cc = v cc (min) v oh v out or v out v ol(max) v oh v out or v out v ol (max) condition min. typ. max. units 2.8 2.0 -0.3 0.2 5.25 0.8 v 0.55 v v 2.4 v v ccio i/o reference voltage 3.0 3.6 v v v select devices discontinued 10 specifications ispgdx160va dc electrical characteristics for 2.5v range 1 over recommended operating conditions v ih symbol 2.5v/gdx160va v oh parameter input high voltage output high voltage v oh(min) v out or v out v ol(max) v oh(min) v out or v out v ol(max) v ccio=min , i oh = -8ma v ccio=min , i ol = 8ma condition min. typ. max. units 1.7 1.8 5.25 v v ccio v il i/o reference voltage input low voltage 2.3 -0.3 2.7 0.7 v v v v ccio=min , i oh = -100a 2.1 v 0.6 v v ccio=min , i ol = 100a 0.2 v v ol output low voltage 1. i/o voltage configuration must be set to vccio. dc electrical characteristics over recommended operating conditions symbol 1. one output at a time for a maximum of one second. v out = 0.5v was selected to avoid test problems by tester ground degradation. characterized, but not 100% tested. 2. typical values are at v cc = 3.3v and t a = 25c. 3. i cc / mhz = (0.003 x i/o cell fanout) + 0.029. e.g. an input driving four i/o cells at 40mhz results in a dynamic i cc of approximately ((0.003 x 4) + 0.029) x 40 = 1.64ma. 4. for a typical application with 50% of i/o pins used as inputs, 50% used as outputs or bi-directionals. 5. this parameter limits the total current sinking of i/o pins surrounding the nearest gnd pin. dc char_gdx160va i pu i bhls parameter i/o active pullup current bus hold low sustaining current i ih i il input or i/o high leakage current input or i/o low leakage current 0v v in v il (max) condition min. typ. 2 max. units -10 10 -200 50 a i bht bus hold trip points v il ? ih v a a a 40 a (v ccio -0.2) v in v ccio v ccio v in 5.25v 0v v in v il (max) i os 1 output short circuit current -250 ma v cc = 3.3v, v out = 0.5v, t a = 25c i ccq 4 quiescent power supply current 16.5 ma v il = 0.5v, v ih = v cc v in = v il (max) i bhhs bus hold high sustaining current -40 a v in = v ih (min) i bhlo bus hold low overdrive current 550 a 0v v in v ccio i cc dynamic power supply current per input switching one input toggling at 50% duty cycle, outputs open. see note 3 ma/ mhz i cont 5 maximum continuous i/o pin sink current through any gnd pin 160 ma i bhho bus hold high overdrive current -550 a 0v v in v ccio select devices discontinued 11 specifications ispgdx160va 5.0 5.0 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 14.0 5.0 0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data prop. delay from any i/o pin to any i/o pin (4:1 mux) data prop. delay from muxsel inputs to any output (4:1 mux) clock frequency, max. toggle clock frequency with external feedback input latch or register setup time before y x input latch or register setup time before i/o clock output latch or register setup time before y x output latch or register setup time before i/o clock global clock enable setup time before y x global clock enable setup time before i/o clock i/o clock enable setup time before y x input latch or reg. hold time (y x ) input latch or reg. hold time (i/o clock) output latch or reg. hold time (y x ) output latch or reg. hold time (i/o clock) global clock enable hold time (y x ) global clock enable hold time (i/o clock) i/o clock enable hold time (y x ) output latch or reg. clock (from y x ) to output delay input latch or register clock (from y x ) to output delay output latch or reg ister clock ( from i/o pin) to output delay input latch or register clock (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clock pulse duration, high clock pulse duration, low register reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) external timing parameters over recommended operating conditions ns ns mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 3.5 3.5 10.0 a a a a a a b c b c d a t pd 2 t sel 2 f max (tog.) f max (ext.) t su1 t su2 t su3 t su4 t suce1 t suce2 t suce3 t h1 t h2 t h3 t h4 t hce1 t hce2 t hce3 t gco1 2 t gco2 2 t co1 2 t co2 2 t en 2 t dis 2 t toeen 2 t toedis 2 t wh t wl t rst t rw t sl t sk description parameter ( ) 1 tsu3+tgco1 units -5 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . 2. the delay parameters are measured with vcc as i/o voltage reference. an additional 0.5ns delay is incurred when vccio is used as i/o voltage reference. # 3.5 3.5 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 8.0 3.5 0.5 250 166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 2.0 2.0 5.0 -3 min. max. test 1 cond. select devices discontinued 12 specifications ispgdx160va 9.0 9.0 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 22.0 9.0 1.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data prop. delay from any i/o pin to any i/o pin (4:1 mux) data prop. delay from muxsel inputs to any output (4:1 mux) clock frequency, max. toggle clock frequency with external feedback input latch or register setup time before y x input latch or register setup time before i/o clock output latch or register setup time before y x output latch or register setup time before i/o clock global clock enable setup time before y x global clock enable setup time before i/o clock i/o clock enable setup time before y x input latch or reg. hold time (y x ) input latch or reg. hold time (i/o clock) output latch or reg. hold time (y x ) output latch or reg. hold time (i/o clock) global clock enable hold time (y x ) global clock enable hold time (i/o clock) i/o clock enable hold time (y x ) output latch or reg. clock (from y x ) to output delay input latch or register clock (from y x ) to output delay output latch or reg ister clock ( from i/o pin) to output delay input latch or register clock (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clock pulse duration, high clock pulse duration, low register reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) external timing parameters over recommended operating conditions ns ns mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 83 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 6.0 6.0 18.0 a a a a a a b c b c d a t pd 2 t sel 2 f max (tog.) f max (ext.) t su1 t su2 t su3 t su4 t suce1 t suce2 t suce3 t h1 t h2 t h3 t h4 t hce1 t hce2 t hce3 t gco1 2 t gco2 2 t co1 2 t co2 2 t en 2 t dis 2 t toeen 2 t toedis 2 t wh t wl t rst t rw t sl t sk description parameter ( ) 1 tsu3+tgco1 units -9 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . 2. the delay parameters are measured with vcc as i/o voltage reference. an additional 0.5ns delay is incurred when vccio is used as i/o voltage reference. # -7 min. max. test 1 cond. 100 80 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 5.0 5.0 14.0 7.0 7.0 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 18.0 7.0 0.5 select devices discontinued 13 specifications ispgdx160va external timing parameters (continued) 1.0 0.0 04 10 20 30 40 50 60 70 0.2 0.4 0.6 0.8 1.2 1.4 1.6 ? grp delay (ns) i/o cell fanout ispgdx160va maximum ? grp delay vs. i/o cell fanout ispgdx160va timings are specified with a grp load (fanout) of four i/o cells. the figure below shows the ? grp delay with increased grp loads. these deltas apply to any signal path traversing the grp (muxa-d, oe, clk/clken, muxsel0-1). global clock signals which do not use the grp have no fanout delay adder. select devices discontinued 14 specifications ispgdx160va -3 -5 parameter # description 1 min. max. min. max. units inputs t io 32 input buffer delay 0.4 0.9 ns grp t grp 33 grp delay 1.1 1.1 ns mux t muxd 34 i/o cell mux a/b/c/d data delay 1.0 1.5 ns t muxexp 35 i/o cell mux a/b/c/d expander delay 1.5 2.0 ns t muxs 36 i/o cell data select 1.0 1.5 ns t muxsio 37 i/o cell data select (i/o clock) 1.5 3.0 ns t muxsg 38 i/o cell data select (yx clock) 1.5 2.0 ns t muxselexp 39 i/o cell mux data select expander delay 1.5 2.0 ns register t iolat 40 i/o latch delay 1.0 1.0 ns t iosu 41 i/o register setup time before clock 0.8 2.0 ns t ioh 42 i/o register hold time after clock 1.7 1.5 ns t ioco 43 i/o register clock to output delay 1.2 0.5 ns t ior 44 i/o reset to output delay 1.0 1.5 ns t cesu 45 i/o clock enable setup time before clock 2.3 2.0 ns t ceh 46 i/o clock enable hold time after clock 0.2 0.5 ns data path t fdbk 47 i/o register feedback delay 0.6 0.9 ns t iobp 48 i/o register bypass delay 0.0 0.0 ns t ioob 49 i/o register output buffer delay 0.0 0.0 ns t muxcg 50 i/o register a/b/c/d data input mux delay (yx clock) 1.5 2.0 ns t muxcio 51 i/o register a/b/c/d data input mux delay (i/o clock) 1.5 3.0 ns t iodg 52 i/o register i/o mux delay (yx clock) 3.5 4.0 ns t iodio 53 i/o register i/o mux delay (i/o clock) 3.5 5.0 ns outputs t ob 54 output buffer delay 1.0 1.5 ns t obs 55 output buffer delay (slow slew option) 4.5 6.5 ns t oeen 56 i/o cell oe to output enable 3.5 4.0 ns t oedis 57 i/o cell oe to output disable 3.5 4.0 ns t goe 58 grp output enable and disable delay 0.0 0.0 ns t toe 59 test oe enable and disable delay 2.5 2.0 ns clocks t ioclk 60 i/o clock delay 0.3 2.0 ns t gclk 61 global clock delay 1.3 2.0 ns t gclkeng 62 global clock enable (yx clock) 1.5 2.5 ns t gclkenio 63 global clock enable (i/o clock) 1.0 3.5 ns t ioclkeng 64 i/o clock enable (yx clock) 0.5 2.5 ns global reset t gr 65 global reset to i/o register latch 6.0 11.0 ns internal timing parameters 1 over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. refer to the timing model in this data sheet for further details. select devices discontinued 15 specifications ispgdx160va -7 -9 parameter # description 1 min. max. min. max. units inputs t io 32 input buffer delay 1.4 1.9 ns grp t grp 33 grp delay 1.1 1.1 ns mux t muxd 34 i/o cell mux a/b/c/d data delay 2.0 2.5 ns t muxexp 35 i/o cell mux a/b/c/d expander delay 2.5 3.0 ns t muxs 36 i/o cell data select 2.0 2.5 ns t muxsio 37 i/o cell data select (i/o clock) 4.5 6.0 ns t muxsg 38 i/o cell data select (yx clock) 2.5 3.0 ns t muxselexp 39 i/o cell mux data select expander delay 2.5 3.0 ns register t iolat 40 i/o latch delay 1.0 1.0 ns t iosu 41 i/o register setup time before clock 3.2 4.4 ns t ioh 42 i/o register hold time after clock 2.3 2.6 ns t ioco 43 i/o register clock to output delay 0.5 0.5 ns t ior 44 i/o reset to output delay 1.5 1.5 ns t cesu 45 i/o clock enable setup time before clock 2.5 2.0 ns t ceh 46 i/o clock enable hold time after clock 1.0 2.0 ns data path t fdbk 47 i/o register feedback delay 1.2 1.3 ns t iobp 48 i/o register bypass delay 0.3 0.6 ns t ioob 49 i/o register output buffer delay 0.6 0.7 ns t muxcg 50 i/o register a/b/c/d data input mux delay (yx clock) 2.5 3.0 ns t muxcio 51 i/o register a/b/c/d data input mux delay (i/o clock) 4.5 6.0 ns t iodg 52 i/o register i/o mux delay (yx clock) 5.0 6.0 ns t iodio 53 i/o register i/o mux delay (i/o clock) 7.0 9.0 ns outputs t ob 54 output buffer delay 2.2 2.9 ns t obs 55 output buffer delay (slow slew option) 9.2 11.9 ns t oeen 56 i/o cell oe to output enable 6.0 7.5 ns t oedis 57 i/o cell oe to output disable 6.0 7.5 ns t goe 58 grp output enable and disable delay 0.0 0.0 ns t toe 59 test oe enable and disable delay 2.5 3.0 ns clocks t ioclk 60 i/o clock delay 3.2 4.4 ns t gclk 61 global clock delay 2.7 3.4 ns t gclkeng 62 global clock enable (yx clock) 3.7 5.4 ns t gclkenio 63 global clock enable (i/o clock) 5.7 8.4 ns t ioclkeng 64 i/o clock enable (yx clock) 4.2 6.4 ns global reset t gr 65 global reset to i/o register latch 13.7 16.4 ns internal timing parameters 1 over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. refer to the timing model in this data sheet for further details. select devices discontinued 16 specifications ispgdx160v absolute maximum ratings 1,2 supply voltage v cc ................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating conditions c symbol table 2 - 0006 c parameter dedicated clock capacitance 10 units typical test conditions 1 2 8 i/o capacitance pf pf v = 3.3v, v = 2.0v v = 3.3v, v = 2.0v cc cc y i/o capacitance (t a =25 o c, f=1.0 mhz) t a = 0c to +70c t a = -40c to +85c symbol table 2-0005/gdxv v cc v ih 1 v il 1 parameter supply voltage input high voltage 1. typical 100mv of input hysteresis. input low voltage min. max. units 3.0 3.0 2.0 -0.3 3.6 3.6 5.25 0.8 v v v v commercial industrial parameter minimum maximum units erase/reprogram cycles 10,000 cycles erase/reprogram specifications select devices discontinued 17 specifications ispgdx160v output low voltage output high voltage input or i/o low leakage current input or i/o high leakage current i/o active pull-up current bus hold low sustaining current bus hold high sustaining current bus hold low overdrive current bus hold high overdrive current bus hold trip points output short circuit current quiescent power supply current dynamic power supply current per input switching maximum continuous i/o pin sink current through any gnd pin i ol =24 ma i oh =-12 ma 0v v in v il (max.) v cc v in 5.25v 0v v in v il v in = v il (max.) v in = v ih (min.) 0v v in v cc 0v v in v cc v cc = 3.3v, v out = 0.5v, t a = 25?c v il = 0.5v, v ih = v cc one input toggling @ 50% duty cycle, outputs open. 70 2.4 50 -50 v il 0.55 -10 10 -150 550 -550 v ih -250 96 switching test conditions dc electrical characteristics over recommended operating conditions v v a a a a a a a v ma ma ma/mhz ma v ol v oh i il i ih i il-pu i bhls i bhhs i bhlo i bhho i bht i os 1 i ccq 4 i cc 1. one output at a time for a maximum duration of one second. v out = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. typical values are at v cc = 3.3v and t a = 25 o c. 3. i cc / mhz = (0.01 x i/o cell fanout) + 0.04 e.g. an input driving four i/o cells at 40 mhz results in a dynamic i cc of approximately ((0.01 x 4) + 0.04) x 40 = 3.2 ma. 4. for a typical application with 50% of i/o pins used as inputs, 50% used as outputs or bidirectionals. 5. this parameter limits the total current sinking of i/o pins surrounding the nearest gnd pin. symbol min. max. typ. 2 parameter condition units input pulse levels gnd to 3.0v input rise and fall time 1.5ns 10% to 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure at right 3-state levels are measured 0.5v from steady-state active level. + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. see note 3 i cont 5 output load conditions test condition r1 r2 cl a 153? 134? 35pf b 134? 35pf 153? 35pf active high slow slew active low c d 153? 5pf 35pf 134? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004a select devices discontinued 18 specifications ispgdx160v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 data prop. delay from any i/o pin to any i/o pin (4:1 mux) data prop. delay from muxsel inputs to any output (4:1 mux) clock frequency, max. toggle clock frequency with external feedback input latch or register setup time before y x input latch or register setup time before i/o clock output latch or register setup time before y x output latch or register setup time before i/o clock global clock enable setup time before y x global clock enable setup time before i/o clock i/o clock enable setup time before y x input latch or register hold time (y x ) input latch or register hold time (i/o clock) output latch or register hold time (y x ) output latch or register hold time (i/o clock) global clock enable hold time (y x ) global clock enable hold time (i/o clock) i/o clock enable hold time (y x ) output latch or register clock (from y x ) to output delay input latch or register clock (from y x ) to output delay output latch or register clock (from i/o pin) to output delay input latch or register clock (from i/o pin) to output delay input to output enable input to output disable test oe output enable test oe output disable clock pulse duration, high clock pulse duration, low register reset delay from reset low reset pulse width output delay adder for output timings using slow slew rate output skew (tgco1 across chip) external timing parameters over recommended operating conditions ns ns mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 143 110 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 3.5 3.5 10.0 5.0 6.5 5.0 8.5 6.0 9.5 6.0 6.0 9.0 9.0 14.0 8.0 0.5 100 80.0 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 5.0 5.0 14.0 7.0 9.0 7.0 11.0 9.0 13.0 8.5 8.5 12.0 12.0 18.0 12.0 0.5 a a a a a a b c b c d a t pd t sel f max (tog.) f max (ext.) t su1 t su2 t su3 t su4 t suce1 t suce2 t suce3 t h1 t h2 t h3 t h4 t hce1 t hce2 t hce3 t gco1 t gco2 t co1 t co2 t en t dis t toeen t toedis t wh t wl t rst t rw t sl t sk description parameter test 1 cond. ( ) 1 tsu3+tgco1 units -5 min. max. -7 min. max. 1. all timings measured with one output switching, fast output slew rate setting, except t sl . # select devices discontinued 19 specifications ispgdx160v external timing parameters (continued) 1.0 0.0 04 10 20 30 40 50 60 70 0.2 0.4 0.6 0.8 1.2 1.4 1.6 ? grp delay (ns) i/o cell fanout ispgdx160v maximum ? grp delay vs. i/o cell fanout ispgdx160v timings are specified with a grp load (fanout) of four i/o cells. the figure below shows the ? grp delay with increased grp loads. these deltas apply to any signal path traversing the grp (muxa-d, oe, clk/clken, muxsel0-1). global clock signals which do not use the grp have no fanout delay adder. select devices discontinued 20 specifications ispgdx160v -5 -7 parameter # description 1 min. max. min. max. units inputs t io 32 input buffer delay 0.9 1.4 ns grp t grp 33 grp delay 1.1 1.1 ns mux t muxd 34 i/o cell mux a/b/c/d data delay 1.5 2.0 ns t muxexp 35 i/o cell mux a/b/c/d expander delay 2.0 2.5 ns t muxs 36 i/o cell data select 3.0 4.0 ns t muxsio 37 i/o cell data select (i/o clk) 4.5 6.5 ns t muxsg 38 i/o cell data select (yx clk) 3.5 4.5 ns t muxselexp 39 i/o cell mux data select expander delay 3.5 4.5 ns register t iolat 40 i/o latch delay 1.0 1.0 ns t iosu 41 i/o register setup time before clock 2.0 3.2 ns t ioh 42 i/o register hold time after clock 1.5 2.3 ns t ioco 43 i/o register clock to output delay 0.5 0.5 ns t ior 44 i/o reset to output delay 1.5 1.5 ns t cesu 45 i/o clock enable setup time before clock 2.0 2.5 ns t ceh 46 i/o clock enable hold time after clock 0.5 1.0 ns data path t fdbk 47 i/o register feedback delay 0.9 1.2 ns t iobp 48 i/o register bypass delay 0.0 0.3 ns t ioob 49 i/o register output buffer delay 0.0 0.6 ns t muxcg 50 i/o register a/b/c/d data input mux delay (yx clk) 2.0 2.5 ns t muxcio 51 i/o register a/b/c/d data input mux delay (i/o clk) 3.0 4.5 ns t iodg 52 i/o register i/o mux delay (yx clk) 4.0 5.0 ns t iodio 53 i/o register i/o mux delay (i/o clk) 5.0 7.0 ns outputs t ob 54 output buffer delay 1.5 2.2 ns t obs 55 output buffer delay (slow slew option) 9.5 14.2 ns t oeen 56 i/o cell oe to output enable 4.0 6.0 ns t oedis 57 i/o cell oe to output disable 4.0 6.0 ns t goe 58 grp output enable and disable delay 0.0 0.0 ns t toe 59 test oe enable and disable delay 5.0 6.0 ns clocks t ioclk 60 i/o clock delay 2.0 3.2 ns t gclk 61 global clock delay 2.0 2.7 ns t gclkeng 62 global clock enable (yx clk) 2.5 3.7 ns t gclkenio 63 global clock enable (i/o clk) 3.5 5.7 ns t ioclkeng 64 i/o clock enable (yx clk) 2.5 4.2 ns global reset t gr 65 global reset to i/o register latch 11.0 13.7 ns internal timing parameters 1 over recommended operating conditions 1. internal timing parameters are not tested and are for reference only. 2. refer to the timing model in this data sheet for further details. select devices discontinued 21 specifications ispgdx160v/va switching waveforms clock width clk (i/o input) t wl t wh combinatorial i/o output valid input data (i/o input) t pd t sel valid input muxsel (i/o input) combinatorial output combinatorial i/o output oe (i/o input) t en t dis i/o output enable/disable registered output reset registered i/o output t rst reset t rw i/o pin reset toe y0,1,2,3 y0,1,2,3, enable tgclk #61 tgclkeng #62 tgclkenio #63 mux0 mux1 tgrp #33 mux expander input grp a b c d oe tgoe #58 tmuxexp #35 tmuxselexp #39 tiobp #48 clk clken mux expander output tioob #49 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51 tiod #52, #53 tgr #65 0902/gdx160v/va tio #32 tfdbk #47 tioclk #60 tioclkeg #64 tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46 tob #54 tobs #55 toeen #56 toedis #57 ttoe #59 clk clken dq data (i/o input) registered i/o output clk clken valid input tt h t suce t ceh t co 1/ f max (external fdbk) t gco su ispgdxv timing model select devices discontinued 22 specifications ispgdx160v/va isplever development system the isplever development system supports ispgdx design using a vhdl or verilog language syntax. from creation to in-system programming, the isplever sys- tem is an easy-to-use, self-contained design tool. features vhdl and verilog synthesis support available ispgdx design compiler - design rule checker - i/o connectivity checker - automatic compiler function industry standard jedec file for programming min/max timing report interfaces to popular timing simulators user electronic signature (ues) support detailed log and report files for easy design debug on-line help ? indows xp, windows 2000, windows 98 and windows nt compatible solaris and hp-ux versions available in-system programmability all necessary programming of the ispgdxv/va is done via four ttl level logic interface signals. these four signals are fed into the on-chip programming circuitry where a state machine controls the programming. on-chip programming can be accomplished using an ieee 1149.1 boundary scan protocol. the ieee 1149.1- compliant interface signals are test data in (tdi), test data out (tdo), test clock (tck) and test mode select (tms) control. the epen pin is also used to enable or disable the jtag port. the embedded controller port enable pin (epen) is used to enable the jtag tap controller and in that regard has similar functionality to a trst pin. when the pin is driven high, the jtag tap controller is enabled. this is also true when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. this allows isp programming and bscan testing to take place as specified by the instruction table. when the pin is driven low, the jtag tap controller is driven to a reset state asynchronously. it stays there while the pin is held low. after pulling the pin high the jtag controller becomes active. the intent of this fea- ture is to allow the jtag interface to be directly controlled by the data bus of an embedded controller (hence the name embedded port enable). the epen signal is used as a ?evice select?to prevent spurious programming and/or testing from occuring due to random bit patterns on the data bus. figure 9 illustrates the block diagram for the ispjtag interface. figure 9. ispjtag device programming interface ispgdx 160v/va device tdo tdi tms tck epen ispjtag programming interface isplsi device ispmach device ispgdx 160v/va device ispgdx 160v/va device select devices discontinued 23 specifications ispgdx160v/va boundary scan the ispgdxv/va devices provide ieee1149.1a test capability and isp programming through a standard boundary scan test access port (tap) interface. the boundary scan circuitry on the ispgdxv/va family operates independently of the programmed pattern. this allows customers using boundary scan test to have full test capability with only a single bsdl file. the ispgdxv/va devices are identified by the 32-bit jtag idcode register. the device id assignments are listed in table 4. table 3. i/o shift register order figure 10. boundary scan register circuit for i/o pins normal function oe extest update dr scanout (to next cell) clock dr scanin (from previous cell shift dr normal function toe dq dq dq dq dq i/o pin reset bscan registers bscan latches highz 0 1 0 1 prog_mode extest i/o shift reg order/ispgdxva ispgdx160v/va tdi, toe, y2, y3, reset, y1, y0, i/o b20 .. b39, i/o c0 .. c39, i/o d0 .. d19, i/o b19 .. b0, i/o a39.. a0, i/o d39 .. d20, tdo i/o shift register order device table 4. ispgdx160v/va device id codes id code/gdx160v/va ispgdx160v 0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011 ispgdx160va 0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011 32-bit boundary scan id code device select devices discontinued 24 specifications ispgdx160v/va the ispjtag programming is accomplished by execut- ing lattice private instructions under the boundary scan state machine. details of the programming sequence are transparent to the user and are handled by lattice isp daisy chain 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 1 update-ir exit2-ir pause-ir exit1-ir shift-ir capture-ir select-ir-scan update-dr exit2-dr pause-dr exit1-dr shift-dr capture-dr select-dr-scan run-test/idle test-logic-reset figure 12. boundary scan state machine figure 11. boundary scan register circuit for input-only pins downlowad (ispdcd ), ispcode ??routines or any third-party programmers. contact lattice technical sup- port to obtain more detailed programming information. scanout (to next cell) clock dr scanin (from previous cell shift dr dq input pin boundary scan (continued) select devices discontinued 25 specifications ispgdx160v/va symbol parameter min max units t btcp tck [bscan test] clock pulse width 100 ns t btch tck [bscan test] pulse width high 50 ns t btcl tck [bscan test] pulse width low 50 ns t btsu tck [bscan test] setup time 20 ns t bth tck [bscan test] hold time 25 ns t rf tck [bscan test] rise and fall time 50 mv/ns t btco ta p controller falling edge of clock to valid output 25 ns t btoz ta p controller falling edge of clock to data output disable 25 ns t btvo ta p controller falling edge of clock to data output enable 25 ns t btcpsu bscan test capture register setup time 20 ns t btcph bscan test capture register hold time 25 ns t btuco bscan test update reg, falling edge of clock to valid output 50 ns t btuoz bscan test update reg, falling edge of clock to output disable 50 ns t btuov bscan test update reg, falling edge of clock to output enable 50 ns figure 13. boundary scan waveforms and timing specifications tms tdi tck tdo data to be captured data to be driven out valid data valid data valid data valid data data captured btsu t bth t btcl t btch t btcp t btvo t btco t btoz t btcsu t btch t btuov t btuco t btuoz t boundary scan (continued) select devices discontinued 26 specifications ispgdx160v/va i/o input/output pins ?these are the general purpose bidirectional data pins. when used as outputs, each may be independently latched, registered or tristated. they can also each assume one other control function (oe, clk/clken, and muxsel as described in the text). toe test output enable pin ?this pin tristates all i/p pins when a logic low is driven. reset active low input pin ?resets all i/o register outputs when low. yx/clkenx input pins ?hese can be either global clocks or clock enables. epen input pin ?jtag tap controller enable pin. when high, jtag operation is enabled. when low, jtag tap controller is driven to reset. tdi input pin ?serial data input during isp programming or boundary scan mode. tck input pin ?serial data clock during isp programming or boundary scan mode. tms input pin ?control input during isp programming or boundary scan mode. tdo output pin ?serial data output during isp programming or boundary scan mode. gnd ground (gnd) vcc vcc ?supply voltage (3.3v). vccio 2 input ?this pin is used if optional 2.5v output is to be used. every i/o can independently select either 3.3v or the optional voltage as its output level. if the optional output voltage is not required, this pin must be connected to the vcc supply. programmable pull-up resistors and bus-hold latches only draw current from this supply. nc 1 no connect. signal descriptions signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. ?a?version only. select devices discontinued 27 specifications ispgdx160v/va signal locations: ispgdx160v/va signal 208-pin pqfp 208-ball fpbga 272-ball bga toe 178 d9 a12 reset 185 a8 d10 y0/clken0 75 n8 v10 y1/clken1 76 r8 y10 y2/clken2 180 b9 c11 y3/clken3 181 c9 a11 epen 183 a9 b10 tdi 81 p9 y12 tck 80 t9 u11 tms 79 t8 v11 tdo 78 p8 w11 gnd 6, 15, 25, 35, 44, 54, 63, d4, d13, g7, g8, g9, a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, 77, 91, 100, 110, 119, 129, g10, h7, h8, h9, h10, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, 139, 148, 159, 168, 182, j7, j8, j9, j10, k7, k8, m11, m12, n4, n17, u4, u8, u13, u17 195, 204 k9, k10, n4, n13 vcc 1, 17, 33, 49, 65, 89, 105, e13 1 , f4, f13, l4, l13, c18 1 , d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, 121, 137, 153, 156 1 , 170, m4, m13, n5, n11, n12 u10, u15 184, 193 d5, d6, d12, e4 vccio 156 1 e13 1 c18 1 nc 73, 74, 179 a10, p7, t7 a2, a6, a7, a10, a15, a19, a20, b1, b2, b4, b11, b14, b18, b19, b20, c2, c3, c10, d2, d3, d16, e2, e17, e19, h1, h3, h18, h20, k20, l1, n1, n3, n18 n20, t2, t4, t19, u5, u18, u19, v3, v14, v18, v19, w1, w2, w3, w7, w10, w14, w19, w20, y1, y2, y6, y9, y11, y18, y20 1. vcc on ispgdx160v, vccio on ispgdx160va. select devices discontinued 28 specifications ispgdx160v/va i/o locations: ispgdx160v/va (ordered by i/o signal name and 208-pin pqfp location) i/o control 208 208 272 signal signal pqfp f pbga bga vcc i/o a0 clk/clken 2 b2 e4 i/o a1 oe 3 b1 c1 i/o a2 muxsel1 4 c2 d1 i/o a3 muxsel2 5 a1 e3 gnd i/o a4 clk/clken 7 c1 e1 i/o a5 oe 8 d3 f3 i/o a6 muxsel1 9 d2 g4 i/o a7 muxsel2 10 d1 f2 i/o a8 clk/clken 11 e3 f1 i/o a9 oe 12 e2 g3 i/o a10 muxsel1 13 e1 g2 i/o a11 muxsel2 14 f3 g1 gnd i/o a12 clk/clken 16 f2 h2 vcc i/o a13 oe 18 f1 j4 i/o a14 muxsel1 19 g4 j3 i/o a15 muxsel2 20 g2 j2 i/o a16 clk/clken 21 g3 j1 i/o a17 oe 22 g1 k2 i/o a18 muxsel1 23 h4 k3 i/o a19 muxsel2 24 h2 k1 gnd i/o a20 clk/clken 26 h3 l2 i/o a21 oe 27 h1 l3 i/o a22 muxsel1 28 j1 l4 i/o a23 muxsel2 29 j3 m1 i/o a24 clk/clken 30 j2 m2 i/o a25 oe 31 j4 m3 i/o a26 muxsel1 32 k1 m4 vcc i/o a27 muxsel2 34 k3 n2 gnd i/o a28 clk/clken 36 k2 p1 i/o a29 oe 37 k4 p2 i/o a30 muxsel1 38 l1 r1 i/o a31 muxsel2 39 l2 p3 i/o a32 clk/clken 40 l3 r2 i/o a33 oe 41 m1 t1 i/o a34 muxsel1 42 m2 p4 i/o a35 muxsel2 43 m3 r3 gnd i/o a36 clk/clken 45 n1 u1 i/o a37 oe 46 n2 t3 i/o a38 muxsel1 47 n3 u2 i/o a39 muxsel2 48 p1 v1 vcc i/o b0 clk/clken 50 p2 u3 i/o b1 oe 51 r1 v2 i/o b2 muxsel1 52 r2 w4 i/o b3 muxsel2 53 t1 v4 gnd i/o b4 clk/clken 55 p3 y3 i/o b5 oe 56 t2 y4 i/o b6 muxsel1 57 r3 v5 i/o b7 muxsel2 58 p4 w5 i/o b8 clk/clken 59 t3 y5 i/o b9 oe 60 r4 v6 i/o b10 muxsel1 61 t4 u7 i/o b11 muxsel2 62 p5 w6 gnd i/o b12 clk/clken 64 r5 v7 vcc i/o b13 oe 66 n6 y7 i/o b14 muxsel1 67 t5 v8 i/o b15 muxsel2 68 r6 w8 i/o b16 clk/clken 69 p6 y8 i/o b17 oe 70 t6 u9 i/o b18 muxsel1 71 n7 v9 i/o b19 muxsel2 72 r7 w9 gnd i/o b20 clk/clken 82 r9 w12 i/o b21 oe 83 n9 v12 i/o b22 muxsel1 84 t10 u12 i/o b23 muxsel2 85 p10 y13 i/o b24 clk/clken 86 r10 w13 i/o b25 oe 87 n10 v13 i/o b26 muxsel1 88 t11 y14 vcc i/o b27 muxsel2 90 p11 y15 gnd i/o b28 clk/clken 92 r11 w15 i/o b29 oe 93 t12 y16 i/o b30 muxsel1 94 p12 u14 i/o b31 muxsel2 95 r12 v15 i/o b32 clk/clken 96 t13 w16 i/o b33 oe 97 r13 y17 i/o b34 muxsel1 98 t14 v16 i/o b35 muxsel2 99 p13 w17 gnd i/o b36 clk/clken 101 r14 u16 i/o b37 oe 102 t15 v17 i/o b38 muxsel1 103 t16 w18 i/o b39 muxsel2 104 r15 y19 vcc i/o c0 clk/clken 106 p14 t17 i/o c1 oe 107 p15 v20 i/o c2 muxsel1 108 r16 u20 i/o c3 muxsel2 109 n14 t18 gnd i/o c4 clk/clken 111 p16 t20 i/o c5 oe 112 n15 r18 i/o c6 muxsel1 113 n16 p17 i/o c7 muxsel2 114 m14 r19 i/o c8 clk/clken 115 m15 r20 i/o c9 oe 116 m16 p18 i/o c10 muxsel1 117 l15 p19 i/o c11 muxsel2 118 l14 p20 gnd i/o c12 clk/clken 120 l16 n19 vcc i/o c13 oe 122 k13 m17 i/o c14 muxsel1 123 k15 m18 i/o c15 muxsel2 124 k14 m19 i/o c16 clk/clken 125 k16 m20 i/o c17 oe 126 j13 l19 i/o c18 muxsel1 127 j15 l18 i/o c19 muxsel2 128 j14 l20 gnd i/o c20 clk/clken 130 j16 k19 i/o c21 oe 131 h14 k18 i/o c22 muxsel1 132 h16 k17 i/o c23 muxsel2 133 h15 j20 i/o c24 clk/clken 134 h13 j19 i/o c25 oe 135 g16 j18 i/o c26 muxsel1 136 g14 j17 vcc i/o c27 muxsel2 138 g15 h19 i/o control 208 208 272 signal signal pqfp f pbga bga i/o control 208 208 272 signal signal pqfp fpbga bga gnd i/o c28 clk/clken 140 g13 g20 i/o c29 oe 141 f16 g19 i/o c30 muxsel1 142 f14 f20 i/o c31 muxsel2 143 f15 g18 i/o c32 clk/clken 144 e16 f19 i/o c33 oe 145 e14 e20 i/o c34 muxsel1 146 e15 g17 i/o c35 muxsel2 147 d16 f18 gnd i/o c36 clk/clken 149 c16 d20 i/o c37 oe 150 d15 e18 i/o c38 muxsel1 151 d14 d19 i/o c39 muxsel2 152 c15 c20 vcc i/o d0 clk/clken 154 b16 d18 i/o d1 oe 155 a16 c19 vcc/vccio 1 i/o d2 muxsel1 157 b15 b17 i/o d3 muxsel2 158 a15 c17 gnd i/o d4 clk/clken 160 c14 a18 i/o d5 oe 161 b14 a17 i/o d6 muxsel1 162 a14 c16 i/o d7 muxsel2 163 c13 b16 i/o d8 clk/clken 164 b13 a16 i/o d9 oe 165 a13 c15 i/o d10 muxsel1 166 c12 d14 i/o d11 muxsel2 167 b12 b15 gnd i/o d12 clk/clken 169 d11 c14 vcc i/o d13 oe 171 a12 a14 i/o d14 muxsel1 172 c11 c13 i/o d15 muxsel2 173 b11 b13 i/o d16 clk/clken 174 d10 a13 i/o d17 oe 175 a11 d12 i/o d18 muxsel1 176 b10 c12 i/o d19 muxsel2 177 c10 b12 gnd vcc i/o d20 clk/clken 186 c8 a9 i/o d21 oe 187 b8 b9 i/o d22 muxsel1 188 d8 c9 i/o d23 muxsel2 189 a7 d9 i/o d24 clk/clken 190 c7 a8 i/o d25 oe 191 b7 b8 i/o d26 muxsel1 192 d7 c8 vcc i/o d27 muxsel2 194 a6 b7 gnd i/o d28 clk/clken 196 c6 c7 i/o d29 oe 197 b6 b6 i/o d30 muxsel1 198 a5 a5 i/o d31 muxsel2 199 c5 d7 i/o d32 clk/clken 200 b5 c6 i/o d33 oe 201 a4 b5 i/o d34 muxsel1 202 b4 a4 i/o d35 muxsel2 203 c4 c5 gnd i/o d36 clk/clken 205 a3 a3 i/o d37 oe 206 c3 d5 i/o d38 muxsel1 207 b3 c4 i/o d39 muxsel2 208 a2 b3 note: vcc and gnd pads shown for reference, 1 vcc in ispgdx160v select devices discontinued 29 specifications ispgdx160v/va i/o a3 muxsel2 5 a1 e3 i/o d39 muxsel2 208 a2 b3 i/o d36 clk/clken 205 a3 a3 i/o d33 oe 201 a4 b5 i/o d30 muxsel1 198 a5 a5 i/o d27 muxsel2 194 a6 b7 i/o d23 muxsel2 189 a7 d9 i/o d17 oe 175 a11 d12 i/o d13 oe 171 a12 a14 i/o d9 oe 165 a13 c15 i/o d6 muxsel1 162 a14 c16 i/o d3 muxsel2 158 a15 c17 i/o d1 oe 155 a16 c19 i/o a1 oe 3 b1 c1 i/o a0 clk/clken 2 b2 e4 i/o d38 muxsel1 207 b3 c4 i/o d34 muxsel1 202 b4 a4 i/o d32 clk/clken 200 b5 c6 i/o d29 oe 197 b6 b6 i/o d25 oe 191 b7 b8 i/o d21 oe 187 b8 b9 i/o d18 muxsel1 176 b10 c12 i/o d15 muxsel2 173 b11 b13 i/o d11 muxsel2 167 b12 b15 i/o d8 clk/clken 164 b13 a16 i/o d5 oe 161 b14 a17 i/o d2 muxsel1 157 b15 b17 i/o d0 clk/clken 154 b16 d18 i/o a4 clk/clken 7 c1 e1 i/o a2 muxsel1 4 c2 d1 i/o d37 oe 206 c3 d5 i/o d35 muxsel2 203 c4 c5 i/o d31 muxsel2 199 c5 d7 i/o d28 clk/clken 196 c6 c7 i/o d24 clk/clken 190 c7 a8 i/o d20 clk/clken 186 c8 a9 i/o d19 muxsel2 177 c10 b12 i/o d14 muxsel1 172 c11 c13 i/o d10 muxsel1 166 c12 d14 i/o d7 muxsel2 163 c13 b16 i/o d4 clk/clken 160 c14 a18 i/o c39 muxsel2 152 c15 c20 i/o c36 clk/clken 149 c16 d20 i/o a7 muxsel2 10 d1 f2 i/o a6 muxsel1 9 d2 g4 i/o a5 oe 8 d3 f3 i/o d26 muxsel1 192 d7 c8 i/o d22 muxsel1 188 d8 c9 i/o d16 clk/clken 174 d10 a13 i/o d12 clk/clken 169 d11 c14 i/o c38 muxsel1 151 d14 d19 i/o c37 oe 150 d15 e18 i/o c35 muxsel2 147 d16 f18 i/o a10 muxsel1 13 e1 g2 i/o a9 oe 12 e2 g3 i/o a8 clk/clk_en 11 e3 f1 i/o c33 oe 145 e14 e20 i/o c34 muxsel1 146 e15 g17 i/o c32 clk/clken 144 e16 f19 i/o a13 oe 18 f1 j4 i/o a12 clk/clken 16 f2 h2 i/o a11 muxsel2 14 f3 g1 i/o c30 muxsel1 142 f14 f20 i/o c31 muxsel2 143 f15 g18 i/o c29 oe 141 f16 g19 i/o a17 oe 22 g1 k2 i/o a15 muxsel2 20 g2 j2 i/o a16 clk/clken 21 g3 j1 i/o a14 muxsel1 19 g4 j3 i/o c28 clk/clken 140 g13 g20 i/o c26 muxsel1 136 g14 j17 i/o c27 muxsel2 138 g15 h19 i/o c25 oe 135 g16 j18 i/o a21 oe 27 h1 l3 i/o a19 muxsel2 24 h2 k1 i/o a20 clk/clken 26 h3 l2 i/o a18 muxsel1 23 h4 k3 i/o c24 clk/clken 134 h13 j19 i/o c21 oe 131 h14 k18 i/o c23 muxsel2 133 h15 j20 i/o c22 muxsel1 132 h16 k17 i/o a22 muxsel1 28 j1 l4 i/o a24 clk/clken 30 j2 m2 i/o a23 muxsel2 29 j3 m1 i/o a25 oe 31 j4 m3 i/o c17 oe 126 j13 l19 i/o c19 muxsel2 128 j14 l20 i/o c18 muxsel1 127 j15 l18 i/o c20 clk/clken 130 j16 k19 i/o a26 muxsel1 32 k1 m4 i/o a28 clk/clken 36 k2 p1 i/o a27 muxsel2 34 k3 n2 i/o a29 oe 37 k4 p2 i/o c13 oe 122 k13 m17 i/o c15 muxsel2 124 k14 m19 i/o c14 muxsel1 123 k15 m18 i/o c16 clk/clken 125 k16 m20 i/o a30 muxsel1 38 l1 r1 i/o a31 muxsel2 39 l2 p3 i/o a32 clk/clken 40 l3 r2 i/o c11 muxsel2 118 l14 p20 i/o c10 muxsel1 117 l15 p19 i/o c12 clk/clken 120 l16 n19 i/o a33 oe 41 m1 t1 i/o a34 muxsel1 42 m2 p4 i/o a35 muxsel2 43 m3 r3 i/o c7 muxsel2 114 m14 r19 i/o locations: ispgdx160v/va (ordered by 208-ball bga location) i/o control 208 208 272 signal signal pqfp f pbga bga i/o control 208 208 272 signal signal pqfp f pbga bga i/o control 208 208 272 signal signal pqfp fpbga bga i/o c8 clk 115 m15 r20 i/o c9 oe 116 m16 p18 i/o a36 clk/clken 45 n1 u1 i/o a37 oe 46 n2 t3 i/o a38 muxsel1 47 n3 u2 i/o b13 oe 66 n6 y7 i/o b18 muxsel1 71 n7 v9 i/o b21 oe 83 n9 v12 i/o b25 oe 87 n10 v13 i/o c3 muxsel2 109 n14 t18 i/o c5 oe 112 n15 r18 i/o c6 muxsel1 113 n16 p17 i/o a39 muxsel2 48 p1 v1 i/o b0 clk/clken 50 p2 u3 i/o b4 clk/clken 55 p3 y3 i/o b7 muxsel2 58 p4 w5 i/o b11 muxsel2 62 p5 w6 i/o b16 clk/clken 69 p6 y8 i/o b23 muxsel2 85 p10 y13 i/o b27 muxsel2 90 p11 y15 i/o b30 muxsel1 94 p12 u14 i/o b35 muxsel2 99 p13 w17 i/o c0 clk/clken 106 p14 t17 i/o c1 oe 107 p15 v20 i/o c4 clk/clken 111 p16 t20 i/o b1 oe 51 r1 v2 i/o b2 muxsel1 52 r2 w4 i/o b6 muxsel1 57 r3 v5 i/o b9 oe 60 r4 v6 i/o b12 clk/clken 64 r5 v7 i/o b15 muxsel2 68 r6 w8 i/o b19 muxsel2 72 r7 w9 i/o b20 clk/clken 82 r9 w12 i/o b24 clk/clken 86 r10 w13 i/o b28 clk/clken 92 r11 w15 i/o b31 muxsel2 95 r12 v15 i/o b33 oe 97 r13 y17 i/o b36 clk/clken 101 r14 u16 i/o b39 muxsel2 104 r15 y19 i/o c2 muxsel1 108 r16 u20 i/o b3 muxsel2 53 t1 v4 i/o b5 oe 56 t2 y4 i/o b8 clk/clken 59 t3 y5 i/o b10 muxsel1 61 t4 u7 i/o b14 muxsel1 67 t5 v8 i/o b17 oe 70 t6 u9 i/o b22 muxsel1 84 t10 u12 i/o b26 muxsel1 88 t11 y14 i/o b29 oe 93 t12 y16 i/o b32 clk/clken 96 t13 w16 i/o b34 muxsel1 98 t14 v16 i/o b37 oe 102 t15 v17 i/o b38 muxsel1 103 t16 w18 select devices discontinued 30 specifications ispgdx160v/va i/o c32 clk/clken 144 e16 f19 i/o c30 muxsel1 142 f14 f20 i/o a11 muxsel2 14 f3 g1 i/o a10 muxsel1 13 e1 g2 i/o a9 oe 12 e2 g3 i/o a6 muxsel1 9 d2 g4 i/o c34 muxsel1 146 e15 g17 i/o c31 muxsel2 143 f15 g18 i/o c29 oe 141 f16 g19 i/o c28 clk/clken 140 g13 g20 i/o a12 clk/clken 16 f2 h2 i/o c27 muxsel2 138 g15 h19 i/o a16 clk/clken 21 g3 j1 i/o a15 muxsel2 20 g2 j2 i/o a14 muxsel1 19 g4 j3 i/o a13 oe 18 f1 j4 i/o c26 muxsel1 136 g14 j17 i/o c25 oe 135 g16 j18 i/o c24 clk/clken 134 h13 j19 i/o c23 muxsel2 133 h15 j20 i/o a19 muxsel2 24 h2 k1 i/o a17 oe 22 g1 k2 i/o a18 muxsel1 23 h4 k3 i/o c22 muxsel1 132 h16 k17 i/o c21 oe 131 h14 k18 i/o c20 clk/clken 130 j16 k19 i/o a20 clk/clken 26 h3 l2 i/o a21 oe 27 h1 l3 i/o a22 muxsel1 28 j1 l4 i/o c18 muxsel1 127 j15 l18 i/o c17 oe 126 j13 l19 i/o c19 muxsel2 128 j14 l20 i/o a23 muxsel2 29 j3 m1 i/o a24 clk/clken 30 j2 m2 i/o a25 oe 31 j4 m3 i/o a26 muxsel1 32 k1 m4 i/o c13 oe 122 k13 m17 i/o c14 muxsel1 123 k15 m18 i/o c15 muxsel2 124 k14 m19 i/o c16 clk/clken 125 k16 m20 i/o a27 muxsel2 34 k3 n2 i/o c12 clk/clken 120 l16 n19 i/o a28 clk/clken 36 k2 p1 i/o a29 oe 37 k4 p2 i/o a31 muxsel2 39 l2 p3 i/o a34 muxsel1 42 m2 p4 i/o c6 muxsel1 113 n16 p17 i/o c9 oe 116 m16 p18 i/o c10 muxsel1 117 l15 p19 i/o c11 muxsel2 118 l14 p20 i/o a30 muxsel1 38 l1 r1 i/o a32 clk/clken 40 l3 r2 i/o a35 muxsel2 43 m3 r3 i/o d36 clk/clken 205 a3 a3 i/o d34 muxsel1 202 b4 a4 i/o d30 muxsel1 198 a5 a5 i/o d24 clk/clken 190 c7 a8 i/o d20 clk/clken 186 c8 a9 i/o d16 clk/clken 174 d10 a13 i/o d13 oe 171 a12 a14 i/o d8 clk/clken 164 b13 a16 i/o d5 oe 161 b14 a17 i/o d4 clk/clken 160 c14 a18 i/o d39 muxsel2 208 a2 b3 i/o d33 oe 201 a4 b5 i/o d29 oe 197 b6 b6 i/o d27 muxsel2 194 a6 b7 i/o d25 oe 191 b7 b8 i/o d21 oe 187 b8 b9 i/o d19 muxsel2 177 c10 b12 i/o d15 muxsel2 173 b11 b13 i/o d11 muxsel2 167 b12 b15 i/o d7 muxsel2 163 c13 b16 i/o d2 muxsel1 157 b15 b17 i/o a1 oe 3 b1 c1 i/o d38 muxsel1 207 b3 c4 i/o d35 muxsel2 203 c4 c5 i/o d32 clk/clken 200 b5 c6 i/o d28 clk/clken 196 c6 c7 i/o d26 muxsel1 192 d7 c8 i/o d22 muxsel1 188 d8 c9 i/o d18 muxsel1 176 b10 c12 i/o d14 muxsel1 172 c11 c13 i/o d12 clk/clken 169 d11 c14 i/o d9 oe 165 a13 c15 i/o d6 muxsel1 162 a14 c16 i/o d3 muxsel2 158 a15 c17 i/o d1 oe 155 a16 c19 i/o c39 muxsel2 152 c15 c20 i/o a2 muxsel1 4 c2 d1 i/o d37 oe 206 c3 d5 i/o d31 muxsel2 199 c5 d7 i/o d23 muxsel2 189 a7 d9 i/o d17 oe 175 a11 d12 i/o d10 muxsel1 166 c12 d14 i/o d0 clk/clken 154 b16 d18 i/o c38 muxsel1 151 d14 d19 i/o c36 clk/clken 149 c16 d20 i/o a4 clk/clk_en 7 c1 e1 i/o a3 muxsel2 5 a1 e3 i/o a0 clk/clken 2 b2 e4 i/o c37 oe 150 d15 e18 i/o c33 oe 145 e14 e20 i/o a8 clk/clken 11 e3 f1 i/o a7 muxsel2 10 d1 f2 i/o a5 oe 8 d3 f3 i/o c35 muxsel2 147 d16 f18 i/o locations: ispgdx160v/va (ordered by 272-ball bga location) i/o control 208 208 272 signal signal pqfp f pbga bga i/o control 208 208 272 signal signal pqfp f pbga bga i/o control 208 208 272 signal signal pqfp fpbga bga i/o c5 oe 112 n15 r18 i/o c7 muxsel2 114 m14 r19 i/o c8 clk 115 m15 r20 i/o a33 oe 41 m1 t1 i/o a37 oe 46 n2 t3 i/o c0 clk/clken 106 p14 t17 i/o c3 muxsel2 109 n14 t18 i/o c4 clk/clken 111 p16 t20 i/o a36 clk/clken 45 n1 u1 i/o a38 muxsel1 47 n3 u2 i/o b0 clk/clken 50 p2 u3 i/o b10 muxsel1 61 t4 u7 i/o b17 oe 70 t6 u9 i/o b22 muxsel1 84 t10 u12 i/o b30 muxsel1 94 p12 u14 i/o b36 clk/clken 101 r14 u16 i/o c2 muxsel1 108 r16 u20 i/o a39 muxsel2 48 p1 v1 i/o b1 oe 51 r1 v2 i/o b3 muxsel2 53 t1 v4 i/o b6 muxsel1 57 r3 v5 i/o b9 oe 60 r4 v6 i/o b12 clk/clken 64 r5 v7 i/o b14 muxsel1 67 t5 v8 i/o b18 muxsel1 71 n7 v9 i/o b21 oe 83 n9 v12 i/o b25 oe 87 n10 v13 i/o b31 muxsel2 95 r12 v15 i/o b34 muxsel1 98 t14 v16 i/o b37 oe 102 t15 v17 i/o c1 oe 107 p15 v20 i/o b2 muxsel1 52 r2 w4 i/o b7 muxsel2 58 p4 w5 i/o b11 muxsel2 62 p5 w6 i/o b15 muxsel2 68 r6 w8 i/o b19 muxsel2 72 r7 w9 i/o b20 clk/clken 82 r9 w12 i/o b24 clk/clken 86 r10 w13 i/o b28 clk/clken 92 r11 w15 i/o b32 clk/clken 96 t13 w16 i/o b35 muxsel2 99 p13 w17 i/o b38 muxsel1 103 t16 w18 i/o b4 clk/clken 55 p3 y3 i/o b5 oe 56 t2 y4 i/o b8 clk/clken 59 t3 y5 i/o b13 oe 66 n6 y7 i/o b16 clk/clken 69 p6 y8 i/o b23 muxsel2 85 p10 y13 i/o b26 muxsel1 88 t11 y14 i/o b27 muxsel2 90 p11 y15 i/o b29 oe 93 t12 y16 i/o b33 oe 97 r13 y17 i/o b39 muxsel2 104 r15 y19 select devices discontinued 31 specifications ispgdx160v/va signal configuration: ispgdx160v/va ispgdx160v/va 272-ball bga signal diagram 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a nc 1 nc 1 i/o d4 i/o d5 i/o d8 nc 1 i/o d13 i/o d16 toe y3/ clken3 nc 1 i/o d20 i/o d24 nc 1 nc 1 i/o d30 i/o d34 i/o d36 nc 1 gnd a b nc 1 nc 1 nc 1 i/o d2 i/o d7 i/o d11 nc 1 i/o d15 i/o d19 epen nc 1 i/o d21 i/o d25 i/o d27 i/o d29 i/o d33 nc 1 i/o d39 nc 1 nc 1 b c i/o c39 i/o d1 vccio vcc 2 i/o d3 i/o d6 i/o d9 i/o d12 i/o d14 i/o d18 y2/ clken2 nc 1 i/o d22 i/o d26 i/o d28 i/o d32 i/o d35 i/o d38 nc 1 nc 1 i/o a1 c d i/o c36 i/o c38 i/o d0 gnd nc 1 vcc i/o d10 gnd i/o d17 vcc reset i/o d23 gnd i/o d31 vcc i/o d37 gnd nc 1 nc 1 i/o a2 d e i/o c33 nc 1 i/o c37 nc 1 i/o a0 i/o a3 nc 1 i/o a4 e f i/o c30 i/o c32 i/o c35 vcc vcc i/o a5 i/o a7 i/o a8 f g i/o c28 i/o c29 i/o c31 i/o c34 i/o a6 i/o a9 i/o a10 i/o a11 g h nc 1 i/o c27 nc 1 gnd gnd nc 1 i/o a12 nc 1 h j i/o c23 i/o c24 i/o c25 i/o c26 gnd gnd gnd gnd i/o a13 i/o a14 i/o a15 i/o a16 j k nc 1 i/o c20 i/o c21 i/o c22 gnd gnd gnd gnd vcc i/o a18 i/o a17 i/o a19 k l i/o c19 i/o c17 i/o c18 vcc gnd gnd gnd gnd i/o a22 i/o a21 i/o a20 nc 1 l m i/o c16 i/o c15 i/o c14 i/o c13 gnd gnd gnd gnd i/o a26 i/o a25 i/o a24 i/o a23 m n nc 1 i/o c12 nc 1 gnd gnd nc 1 i/o a27 nc 1 n p i/o c11 i/o c10 i/o c9 i/o c6 i/o a34 i/o a31 i/o a29 i/o a28 p r i/o c8 i/o c7 i/o c5 vcc vcc i/o a35 i/o a32 i/o a30 r t i/o c4 nc 1 i/o c3 i/o c0 nc 1 i/o a37 nc 1 i/o a33 t u i/o c2 nc 1 nc 1 gnd i/o b36 vcc i/o b30 gnd i/o b22 tck vcc i/o b17 gnd i/o b10 vcc nc 1 gnd i/o b0 i/o a38 i/o a36 u v i/o c1 nc 1 nc 1 i/o b37 i/o b34 i/o b31 nc 1 i/o b25 i/o b21 tms y0/ clken0 i/o b18 i/o b14 i/o b12 i/o b9 i/o b6 i/o b3 nc 1 i/o b1 i/o a39 v w nc 1 nc 1 i/o b38 i/o b35 i/o b32 i/o b28 nc 1 i/o b24 i/o b20 tdo nc 1 i/o b19 i/o b15 nc 1 i/o b11 i/o b7 i/o b2 nc 1 nc 1 nc 1 w y nc 1 i/o b39 nc 1 i/o b33 i/o b29 i/o b27 i/o b26 i/o b23 tdi nc 1 y1/ clken1 nc 1 i/o b16 i/o b13 nc 1 i/o b8 i/o b5 i/o b4 nc 1 nc 1 y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. ncs are not to be connected to any active signals, vcc or gnd. 2. vccio on ispgdx160va. vcc on ispgdx160v. ispgdx160v/va bottom view select devices discontinued 32 specifications ispgdx160v/va signal configuration: ispgdx160v/va ispgdx160v/va 208-ball fpbga signal diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 i/o d1 i/o d3 i/o d6 i/o d9 i/o d13 i/o d17 nc 1 epen reset i/o d23 i/o d27 i/o d30 i/o d33 i/o d36 i/o d39 i/o a3 a b a i/o d0 i/o d2 i/o d5 i/o d8 i/o d11 i/o d15 i/o d18 y2/ clken2 i/o d21 i/o d25 i/o d29 i/o d32 i/o d34 i/o d38 i/o a0 i/o a1 b c i/o c36 i/o c39 i/o d4 i/o d7 i/o d10 i/o d14 i/o d19 y3/ clken3 i/o d20 i/o d24 i/o d28 i/o d31 i/o d35 i/o d37 i/o a2 i/o a4 c d i/o c35 i/o c37 i/o c38 gnd vcc i/o d12 i/o d16 toe i/o d22 i/o d26 vcc vcc gnd i/o a5 i/o a6 i/o a7 d e i/o c32 i/o c34 i/o c33 vccio/ vcc 2 vcc i/o a8 i/o a9 i/o a10 e f i/o c29 i/o c31 i/o c30 vcc vcc i/o a11 i/o a12 i/o a13 f g i/o c25 i/o c27 i/o c26 i/o c28 gnd gnd gnd gnd i/o a14 i/o a16 i/o a15 i/o a17 g h i/o c22 i/o c23 i/o c21 i/o c24 gnd gnd gnd gnd i/o a18 i/o a20 i/o a19 i/o a21 h j i/o c20 i/o c18 i/o c19 i/o c17 gnd gnd gnd gnd i/o a25 i/o a23 i/o a24 i/o a22 j k i/o c16 i/o c14 i/o c15 i/o c13 gnd gnd gnd gnd i/o a29 i/o a27 i/o a28 i/o a26 k l i/o c12 i/o c10 i/o c11 vcc vcc i/o a32 i/o a31 i/o a30 l m i/o c9 i/o c8 i/o c7 vcc vcc i/o a35 i/o a34 i/o a33 m n i/o c6 i/o c5 i/o c3 gnd vcc vcc i/o b25 i/o b21 y0/ clken0 i/o b18 i/o b13 vcc gnd i/o a38 i/o a37 i/o a36 n p i/o c4 i/o c1 i/o c0 i/o b35 i/o b30 i/o b27 i/o b23 tdi tdo nc 1 i/o b16 i/o b11 i/o b7 i/o b4 i/o b0 i/o a39 p r i/o c2 i/o b39 i/o b36 i/o b33 i/o b31 i/o b28 i/o b24 i/o b20 y1/ clken1 i/o b19 i/o b15 i/o b12 i/o b9 i/o b6 i/o b2 i/o b1 r t i/o b38 i/o b37 i/o b34 i/o b32 i/o b29 i/o b26 i/o b22 tck tms nc 1 i/o b17 i/o b14 i/o b10 i/o b8 i/o b5 i/o b3 t 16 15 14 13 12 11 10 1. ncs are not to be connected to any active signals, vcc or gnd. 2. vccio on ispgdx160va. vcc on ispgdx160v. 9 87654321 ispgdx160v/va bottom view select devices discontinued 33 specifications ispgdx160v/va pin configuration: ispgdx160v/va ispgdx160v/va 208-pin pqfp pinout diagram 1. no connect pins (nc) are not to be connected to any active signal, vcc or gnd. 2. vccio on ispgdx160va. vcc on ispgdx160v. ispgdx160v/va top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vcc i/o a 0 i/o a 1 i/o a 2 i/o a 3 gnd i/o a 4 i/o a 5 i/o a 6 i/o a 7 i/o a 8 i/o a 9 i/o a 10 i/o a 11 gnd i/o a 12 vcc i/o a 13 i/o a 14 i/o a 15 i/o a 16 i/o a 17 i/o a 18 i/o a 19 gnd i/o a 20 i/o a 21 i/o a 22 i/o a 23 i/o a 24 i/o a 25 i/o a 26 vcc i/o a 27 gnd i/o a 28 i/o a 29 i/o a 30 i/o a 31 i/o a 32 i/o a 33 i/o a 34 i/o a 35 gnd i/o a 36 i/o a 37 i/o a 38 i/o a 39 vcc i/o b 0 i/o b 1 i/o b 2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 vccio/vcc 2 i/o d1 i/o d 0 vcc i/o c 39 i/o c 38 i/o c 37 i/o c 36 gnd i/o c 35 i/o c 34 i/o c 33 i/o c 32 i/o c 31 i/o c 30 i/o c 29 i/o c 28 gnd i/o c 27 vcc i/o c 26 i/o c 25 i/o c 24 i/o c 23 i/o c 22 i/o c 21 i/o c 20 gnd i/o c 19 i/o c 18 i/o c 17 i/o c 16 i/o c 15 i/o c 14 i/o c 13 vcc i/o c 12 gnd i/o c 11 i/o c 10 i/o c 9 i/o c 8 i/o c 7 i/o c 6 i/o c 5 i/o c 4 gnd i/o c 3 i/o c 2 i/o c 1 i/o c 0 vcc data control muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 clk/clken oe muxsel1 muxsel2 data control i/o b 3 gnd i/o b 4 i/o b 5 i/o b 6 i/o b 7 i/o b 8 i/o b 9 i/o b 10 i/o b 11 gnd i/o b 12 vcc i/o b 13 i/o b 14 i/o b 15 i/o b 16 i/o b 17 i/o b 18 i/o b 19 1 nc 1 nc clk_en0/y0 clk_en1/y1 gnd tdo tms tck tdi i/o b 20 i/o b 21 i/o b 22 i/o b 23 i/o b 24 i/o b 25 i/o b 26 vcc i/o b 27 gnd i/o b 28 i/o b 29 i/o b 30 i/o b 31 i/o b 32 i/o b 33 i/o b 34 i/o b 35 gnd i/o b 36 i/o b 37 i/o b 38 i/o b 39 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken data control i/o d 39 i/o d 38 i/o d 37 i/o d 36 gnd i/o d 35 i/o d 34 i/o d 33 i/o d 32 i/o d 31 i/o d 30 i/o d 29 i/o d 28 gnd i/o d 27 vcc i/o d 26 i/o d 25 i/o d 24 i/o d 23 i/o d 22 i/o d 21 i/o d 20 reset vcc epen gnd y3/clk_en3 y2/clk_en2 nc 1 toe i/o d 19 i/o d 18 i/o d 17 i/o d 16 i/o d 15 i/o d 14 i/o d 13 vcc i/o d 12 gnd i/o d 11 i/o d 10 i/o d 9 i/o d 8 i/o d 7 i/o d 6 i/o d 5 i/o d 4 gnd i/o d 3 i/o d 2 muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 oe clk/clken muxsel2 muxsel1 data control select devices discontinued 34 specifications ispgdx160v/va part number description table 2-0041a/ispgdxv/a 208-pin pqfp 208-ball fpbga 5 7 ispgdx160va-5q208 208-ball fpbga 5 ispgdx160va-5b208 ispgdxva 272-ball bga 5 ispgdx160va-5b272 208-pin pqfp 3.5 ispgdx160va-3q208 208-ball fpbga 3.5 ispgdx160va-3b208 272-ball bga 3.5 ispgdx160va-3b272 208-pin pqfp 7 ispgdx160va-7q208 ispgdx160va-7b208 272-ball bga 7 ispgdx160va-7b272 208-pin pqfp 208-ball fpbga 5 7 ispgdx160v-5q208 208-ball fpbga 5 ispgdx160v-5b208 ispgdxv* 272-ball bga 5 ispgdx160v-5b272 208-pin pqfp 7 ispgdx160v-7q208 ispgdx160v-7b208 272-ball bga 7 ispgdx160v-7b272 family ordering number package tpd (ns) commercial *use ispgdx160va for new designs. note: the ispgdx160va devices are dual-marked with both commercial and industrial grades. the industrial speed grade is slower, e.g. ispgdx160va-3b208-5i. ordering information conventional packaging device number 160v 160va grade blank = commercial i = industrial ispgdx xxxxx x xxxxx x speed 3 = 3.5ns tpd 5 = 5ns tpd 7 = 7ns tpd 9 = 9ns tpd package q208 = 208-pin pqfp b208 = 208-ball fpbga bn208 = lead-free 208-ball fpbga b272 = 272-ball bga - device family 0212/ispgdxva select devices discontinued 35 specifications ispgdx160v/va ordering information (cont.) table 2-0041c/ispgdxv 208-pin pqfp 208-ball fpbga 5 7 ispgdx160va-5q208i 208-ball fpbga 5 ispgdx160va-5b208i ispgdxva ispgdxv* 272-ball bga 5 ispgdx160va-5b272i 208-pin pqfp 7 ispgdx160va-7q208i 208-pin pqfp 7 ispgdx160v-7q208i ispgdx160va-7b208i 272-ball bga 7 ispgdx160va-7b272i 208-ball fpbga 9 208-pin pqfp 9 ispgdx160va-9q208i ispgdx160va-9b208i 272-ball bga 9 ispgdx160va-9b272i family ordering number package tpd (ns) industrial *use ispgdx160va for new designs. note: the ispgdx160va devices are dual-marked with both commercial and industrial grades. the industrial speed grade is slower, e.g. ispgdx160va-3b208-5i. conventional packaging (cont.) lead-free packaging ispgdxva lead-free 208-ball fpbga 3.5 ispgdx160va-3bn208 lead-free 208-ball fpbga 5 ispgdx160va-5bn208 lead-free 208-ball fpbga 7 ispgdx160va-7bn208 family ordering number package tpd (ns) commercial lead-free 208-ball fpbga 5 ispgdx160va-5bn208i lead-free 208-ball fpbga 7 ispgdx160va-7bn208i ispgdxva lead-free 208-ball fpbga 9 ispgdx160va-9bn208i family ordering number package tpd (ns) industrial note: the ispgdx160va devices are dual-marked with both commercial and industrial grades. the industrial speed grade is slower, e.g. ispgdx160va-3b208-5i. select devices discontinued |
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